1. Field of the Invention
This invention relates to the design of on-chip circuitry for testing semiconductor devices. More specifically, it relates to a method and apparatus for performing voltage sub-sampling of weakly-driven nodes of a semiconductor device.
2. Description of the Relevant Art
To understand the functionality of an integrated circuit, it is often useful to monitor the voltage of various signals at specific locations (sometimes referred to as nodes) in the circuit. On-chip sampling circuits have been used to perform non-invasive probing of voltages on a semiconductor chip. Monitoring the voltage of these signals is often accomplished by sampling the signals and then driving the output of the sampler off-chip for observation, such as on one or more pins.
Traditional sampler designs are appropriate for sampling nodes that are directly driven by transistors, but may not be suitable for sampling nodes that are weakly-driven or for sampling floating (rather than actively-driven) nodes. Examples of such nodes include capacitively-driven nodes such as receiver nodes used in proximity communication or low-swing signaling, nodes with weak drivers, or nodes that are far away from their drivers. In these applications, traditional sampler designs may exhibit switching effects that are inconveniently large compared to the amplitude of the sampled signals or they may exhibit unacceptably high leakage currents, clock feed-through, or charge injection effects.